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Edge710 500 MHz Pin Electronics Driver, Window Comparator, and Load
EDGE HIGH-PERFORMANCE PRODUCTS Description
The Edge710 is a totally monolithic ATE pin electronics solution manufactured in a high-performance complementary bipolar process. In Automatic Test Equipment (ATE) applications, the Edge710 incorporates a driver, a load, and a window comparator suitable for very fast bidirectional channels in VLSI, Mixed-Signal, and Memory test systems. The three-statable driver is capable of generating 9V swings over a 12V range. In addition, 13V super voltage may be obtained under certain operating conditions. Separate rise and fall edge adjustments support both high speed and low speed applications, and allow for superior rise and fall time matching. An input power down mode allows extremely low leakage current in HiZ. The load supports programmable source and sink currents of 35 mA over a 12V range, or it can be completely disabled. The source current, sink current, and commutating voltage are all independently set. In addition, the load is configurable and may be used as a programmable voltage clamp. The window comparator spans a 12V common mode range, tracks input signals with edge rates greater than 6 V/ns, and passes sub-ns pulses. An input power down mode allows for extremely low leakage measurements. The inclusion of all pin electronics building blocks into a 52 lead MQFP (10 mm body w/ internal heat spreader) offers a highly integrated solution that is traditionally implemented with multiple integrated circuits or discretes.
Features
* * * * * * * * Fully Integrated Three-Statable Driver, Window Comparator, and Dynamic Active Load 12V Driver, Load, Compare Range 13V Super Voltage Capable 35 mA Programmable Load Comparator Input Tracking >6V/ns Leakage (L+D+C) < 1 A (normal mode) Leakage (L+D+C) < 25 nA (IPD mode) Small footprint (52 pin MQFP)
Functional Block Diagram
BIAS DVH
DHI DHI*
RADJ
DOUT DVR_EN DVR_EN* FADJ
DVL IPD_D QA* QA PECL IPD_C QB QB* CVB VINP CVA
VCC
Applications
* * * * VLSI Test Equipment Mixed-Signal Test Equipment Memory Testers (Bidirectional Channels) ASIC Verifiers
1K
ISC_IN VCM_IN VCM_OUT_A VCM_OUT_B LOAD BRIDGE_SC
1K
ISK_IN LD_EN LD_EN* BRIDGE_SK
VEE
Revision 2 / December 1, 2000
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Edge710
EDGE HIGH-PERFORMANCE PRODUCTS PIN Description
Pin Name Driver DOUT DHI/DHI* DVR_EN/DVR_EN* DVH, DVL DVH_CAP DVL_CAP RADJ, FADJ BIAS IPD_D Comparator VINP CVA, CVB QA/QA* QB/QB* IPD_C PECL Load LOAD LD_EN/LD_EN* VCM_IN ISC_IN, ISK_IN 38 2, 3 44 48, 45 Load Output. Wide voltage differential inputs which activate and disable the load. High impedance analog voltage input that programs the commutating voltage. Analog current inputs which program the load source and sink currents. Should be connected to external voltage or current source through minimum 500 series resistors. Commutating buffer op amp compensation pin. Commutating voltage pins. Diode bridge connections to the output bridge that bypass the internal current sources.
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Pin #
Description
30 12, 13 14, 15 20, 19 24 25 17, 16 18 34
Driver Output. Wide voltage differential input digital pins which determine the driver high or low level. Wide voltage differential input digital pins which control the driver being active or in a high impedance state. High impedance analog voltage inputs which determine the driver high and low level. Op amp compensation pin. A 100 pF capacitor should be connected to DVH. Op amp compensation pin. A 100 pF capacitor should be connected to DVL. Input currents which determine the driver transition times. Analog current input which sets an internal bias current. TTL driver input power down control which slows the driver down and reduces the driver HiZ leakage current.
33 50, 51 6, 5 10, 11 35 7, 8
Analog voltage input to the positive input of comparators. Analog inputs which set the comparator thresholds. Differential ECL (or PECL) digital outputs of comparators A and B. TTL input power down input which slows the comparator down, but significantly reduces the VINP bias current. Unbuffered power supply level for the comparator output stages which establishes either ECL or PECL digital levels.
VCM_CAP VCM_OUT_A VCM_OUT_B BRIDGE_SC BRIDGE_SK
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Edge710
EDGE HIGH-PERFORMANCE PRODUCTS PIN Description (continued)
Pin Name Power Supplies, Miscellaneous CATHODE ANODE VCC VEE GND N/C 27 26 4, 31, 32, 49 1, 28, 29, 52 9, 21, 22, 36, 37, 46, 47 23 Terminals of the on-chip thermal diode string. Pin # Description
Positive power supply level. Negative power supply level. Device Ground. No connect.
VCM_OUT_A VCM_OUT_B
VEE LD_EN LD_EN* VCC QA* QA PECL PECL GND QB QB* DHI DHI*
BRIDGE_SC
VEE CVB CVA VCC ISC_IN GND GND ISK_IN VCM_IN VCM_CAP
52 MQFP 10 mm X 10 mm Top Side
BRIDGE_SK LOAD GND GND IPD_C IPD_D VINP VCC VCC DOUT VEE VEE CATHODE
DVR_EN DVR_EN* FADJ RADJ BIAS DVL DVH GND GND N/C
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DVH_CAP DVL_CAP
ANODE
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Edge710
EDGE HIGH-PERFORMANCE PRODUCTS Circuit Description Driver
Introduction The driver will force DOUT to one of three states: 1. DVH (Drive High) 2. DVL (Drive Low) 3. HiZ (High Impedance). Both driver digital control inputs (DHI / DHI*, DRV_EN / DRV_EN*) are "Flex Inputs" - wide voltage differential inputs capable of receiving ECL, TTL, CMOS, or custom level signals. Single-ended operation is supported by connecting the inverting input to the appropriate DC threshold level. Drive Enable The drive enable (DRV_EN / DRV_EN*) inputs control whether the driver is forcing a voltage, or is placed in a high-impedance state. If DRV_EN is more positive than DRV_EN*, the output will force either DVH or DVL, depending on the driver data input. If DRV_EN is more negative that DRV_EN*, the output goes into a high impedance state. Do NOT leave DRV_EN / DRV_EN* floating. The established bias current follows the equation: Driver Data BIAS = (VCC - 0.7) / (Rext + 1.5). The driver data inputs (DHI / DHI*) determine whether the driver output is forcing a high or a low. If DHI is more positive than DHI*, the driver will force DVH when the driver is active. If DHI is more negative than DHI*, the driver will force DVL when active. Do NOT leave DHI / DHI* floating.
BIAS VCC
Driver Levels DVH and DVL are high input impedance voltage controlled inputs which establish the driver levels of a logical "1" and "0" respectively. Driver Level Buffer Compensation DVH_CAP and DVL_CAP are op amp compensation pins for the high and low level on-chip buffers. Each pin requires a 0.01 F chip capacitor (with good high frequency characteristics) connected to ground. A tight layout with minimal distance between the pin and the capacitor is recommended. Driver Bias The BIAS pin is an analog current input which establishes an on-chip bias current, from which other currents are generated. This current, to some degree, also establishes the overall power consumption and performance of the chip. Ideally, an external current source would be used to minimize any part-to-part performance variation within a test system. However, a precision external resistor tied to a large positive voltage is acceptable. (See figure below.) The optimal BIAS current is a function of the RADJ and FADJ settings, and cannot be set independently.
REXT
Driver Enable DRV_EN > DRV_EN* DRV_EN > DRV_EN* DRV_EN < DRV_EN*
Driver Data DHI > DHI* DHI < DHI* X
DOUT
1.5K
DVH DVL HiZ
VEE
Table 1. Driver Control Truth Table
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Edge710
EDGE HIGH-PERFORMANCE PRODUCTS Circuit Description (continued)
Driver Slew Rate Adjustment The driver rising and falling transition times are independently adjustable. The RADJ and FADJ pins are analog current inputs which establish the driver rise and fall times. Ideally, an external current source would be used for RADJ and FADJ. However, for most applications (where the rise and fall times are fixed), precision external resistors to a positive voltage are acceptable. The currents into RADJ and FADJ follow the equation: RADJ, FADJ = (VCC - 0.7) / (Rext + 1.5).
RADJ (FADJ)
Load
The load is capable of sourcing and sinking at least 35 mA dynamically, or being placed into a high impedance state. The load may also be configured with separate commutating voltage to act as a programmable voltage clamp. In addition, the load may act as a 50 transmission line termination. Load Enable The load enable input determines whether the load is active or in high impedance. If LD_EN is more positive than LD_EN*, the load is active and is capable of sourcing and sinking currents. If LD_EN is more negative than LD_EN*, the load is placed into a high impedance state. LD_EN / LD_EN* are "Flex In" - wide voltage differential inputs capable of receiving ECL, TTL, CMOS, or custom levels. Single-ended operation is supported by connecting the inverting input to the appropriate DC threshold level. Do NOT leave LD_EN / LD_EN* floating.
1.5K
Rise/Fall Adjust Current
Commutating Voltage VCM_IN is a high input impedance analog voltage input which sets the commutating voltage of the load. If LOAD is more positive than VCM_IN, the bridge will sink current from the DUT into the load. If LOAD is more negative than VCM_IN, the load will source current from the load into the DUT.
Input Power Down IPD_D is a TTL compatible input which affects both the driver speed as well as high impedance leakage. With IPD_D = 0, the driver functions normally. With IPD_D = 1, the driver is in IPD mode, where it still functions, although with slower rise and fall times, but with an extremely low HiZ leakage current. Do not leave IPD_D floating !! If IPD_D is not used, connect it to ground.
VCM_IN
DUT
VCM_IN
DUT
LOAD < VCM_IN LOAD > VCM_IN
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Edge710
EDGE HIGH-PERFORMANCE PRODUCTS Circuit Description (continued)
Source and Sink Current Levels The amount of current that the diode bridge can source and sink is adjustable from 0 mA to 35 mA. The source and sink levels are separate and independent. ISC_IN and ISK_IN are current controlled inputs whose voltage level is held very close to ground (<100 mV variation) over the entire legal current input range. There is a nominal gain of 20 between the ISC_IN current and the bridge source current. ISOURCE = 20 * ISC_IN There is a nominal gain of -20 between the ISK_IN current and the bridge sink current. ISINK = -20 * ISK_IN Because the inversion creates a 180 phase shift between ISK_IN and ISINK, there is a tendency toward instability. A minimum of 500 W of external series resistance should be used between an external voltage or current source and the ISC_IN and ISK_IN pins to ensure stability. Stray capacitance at the ISK_IN pin should be kept to a minimum. PCB layout should minimize coupling between ISK_IN and LOAD. Caution: The ISKIN and ISCIN inputs are designed for positive current between 0 mA and 1.75 mA flowing into the part. Care should be taken to insure that current is never required to flow out of the part on these two nodes. Commutating Voltage Compensation The VCM_CAP pin is an op amp compensation node that requires a fixed .01 F chip capacitor (with good high frequency characteristics) to ground. This capacitor is used to compensate an internal node on the on-chip buffer for the commutating voltage input. Split Load The VCM_OUT_A is the actual commutating voltage generated by the on-chip buffer. VCM_OUT_A is also connected to the upper half of the diode bridge, and is responsible for sinking the programmed source current when the load is sinking current from the DUT. VCM_OUT_B is connected to the lower half of the diode bridge, and is responsible for providing the sink current when the load is sourcing current to the DUT. VCM_OUT_B does NOT have an on-chip buffer. To configure the load as a standard active diode bridge, connect VCM_OUT_A and VCM_OUT_B together off-chip. Or, to configure the load as a split load, an external buffer must be used for VCM_OUT_B. External Bridge Connections Access to the top and bottom of the diode bridge is granted through a 1 KW resistor. Pins BRIDGE_SC and BRIDGE_SK allow external current sources to be used instead of the internal I_SOURCE and I_SINK sources. These external pins are useful when extremely accurate source and sink currents are required for low current operation.
I_SOURCE
1K BRIDGE_SC
VCM_IN LOAD
1K BRIDGE_SK I_SINK VCM_OUT_A VCM_OUT_B
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Edge710
EDGE HIGH-PERFORMANCE PRODUCTS Circuit Description (continued) Window Comparator
Two comparators are connected on-chip to form a window comparator to determine whether the DUT is high, low, or in an indeterminant state. VINP is tied to the positive inputs of both comparators. The selection of either comparator A or B for the DUT high versus the DUT low is arbitrary. However, because the positive input is used on both comparators, the comparator used to detect DUT low will have an inversion at it digital outputs. The figure below shows the correct polarity for the comparator connections. The power supply driving the PECL pin must be capable of sourcing all the current flowing out of the QA/QA* and QB/ QB* open emitter outputs.
Comparator Input Protection VINP connect to over-voltage diodes connected to the positive and negative power supplies. These diodes are sized to handle up to 100 mA current. Thermal Monitor An on-chip thermal diode string of five diodes in series exists (see figure below). This string allows accurate die temperature measurements.
QA* QA
CVA
ANODE
IPD_C VINP PECL QB QB* CVB
Bias Current
Temperature Coefficient = -9 mV / C
Thresholds
CVA and CVB are the two comparator threshold levels. These inputs are high impedance voltage controlled inputs that determine at which VINP voltage the comparators will change output states. PECL Level Capability PECL is the power supply level for the output stage of the comparators. When connected to ground, the comparator outputs will be standard ECL outputs. However, by making PECL more positive, QA / QA* and QB / QB* will track PECL and also become more positive. By raising these voltage levels, the comparators may connect directly with CMOS ICs.
CATHODE
An external bias current of 100 A is injected through the string, and the measured voltage corresponds to a specific junction temperature with the following equation: Tj[C] = {(ANODE - CATHODE)/5 - .7752} / (-.0018).
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Edge710
EDGE HIGH-PERFORMANCE PRODUCTS Application Information
Super Voltage Operation The Edge710 may be used to generate a super voltage level up to 13V at the driver output. To generate this high voltage, an analog input mux may be used to switch between the normal high and low drive levels, and a super voltage level.
DVH A Y B
Extremely Low Leakage Usage The Edge710 is capable of supporting total load + drive + comparator leakage ~15 nA. This low leakage mode may be very useful during PMU operation if the pin electronics are not isolated by a relay, thus eliminating the need for 1 relay per pin. To realize this low leakage, the following conditions must be met: 1. IPD_D = 1 (place the driver in "power down" mode) 2. IPD_C = 1 (place the comparator in "power down" mode) 3. CVA, CVB VINP (program the comparator thresholds any expected voltage at the comparator inputs.)
S/V 710 S/V SELECT D_OUT
B Y DVL A
Certain Power Supply conditions must be met to support this functionality.
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Edge710
EDGE HIGH-PERFORMANCE PRODUCTS Package Information
4 D D2 4X 0.25 C A-B D
PIN Descriptions
D
3
3
A E E2 B 3 4
e
SEE DETAIL "A"
TOP VIEW
5 D1 Z D
7
C
O
E1
5
7
O
2 Z 4X E 0.20
5 C
7 A-B D
BOTTOM VIEW
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Edge710
EDGE HIGH-PERFORMANCE PRODUCTS Package Information (continued)
0.40 MIN. 0 MIN.
e
A2 - 0.10 S 0.13 R. MIN. 0.13 / 0.30 R.
C 0.25
GAGE PLANE
-A, B, D-
3
A1 C L 1.60 REF.
DETAIL "A"
0-7
DETAIL "B"
12 - 16
A
SEE DETAIL "B" b
8
ccc
M C A-B S D S WITH LEAD FINISH
1.41 REF.
H
2 0.076
12 0.13 / 0.23
0.13 / 0.17
C 12 - 16
SECTION C-C
b 1
BASE METAL
Notes: 1. All dimensions and tolerances conform to ANSI Y14.5-1982. 2. Datum plane -H- located at mold parting line and coincident with lead, where lead exits plastic body at bottom of parting line. 3. Datums A-B and -D- to be determined where centerline between leads exits plastic body at datum plane -H-. 4. To be determined at seating plane -C-. 5. Dimensions D1 and E1 do not include mold protrusion. Allowable mold protrusion is 0.254 mm per side. Dimensions D1 and E1 do include mold mismatch and are determined at datum plan -H-. 6. "N" is the total # of terminals. 7. Package top dimensions are smaller than bottom dimensions by 0.20 mm, and top of package will not overhang bottom of package. 8. Dimension b does not include dambar protrusion. Allowable dambar protrusion shall be 0.08 mm total in excess of the b dimension at maximum material condition. Dambar cannot be located on the lower radius or the foot. 9. All dimensions are in millimeters. 10. Maximum allowable die thickness to be assembled in this package family is 0.635 millimeters. 11. This drawing conforms to JEDEC registered outline MS-108. 12. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip.
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JEDEC Variation (all dimensions in millimeters)
Symbol A A1 A2 D D1 D2 ZD E E1 E2 ZE L N e b b1 aaa 0.22 0.22 0.30 0.12 0.73 0.10 1.95 Min Nom 2.15 0.15 2.00 13.20 BSC 10.00 BSC 7.80 REF 1.10 REF 13.20 BSC 10.00 BSC 7.80 REF 1.10 REF 0.88 52 0.65 0.38 0.33 8 1.03 6 Pin Count Lead Pitch 4 5 Body Width Max 2.35 0.25 2.10 4 5 Body Length Note Comments Height above PCB PCB Clearance Body Thickness
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Edge710
EDGE HIGH-PERFORMANCE PRODUCTS Recommended Operating Conditions
Parameter Positive Power Supply Negative Power Supply Total Analog Supply Comparator Output Supply Analog Inputs Driver High Level Driver Low Level Super Voltage Levels Slew Rate Adjustments Chip Bias Source, Sink Currents Comparator Thresholds Ambient Operating Temperature Junction Temperature Symbol VCC VEE VCC - VEE PECL DVH DVL DVH, DVL RADJ, FADJ BIAS ISC_IN, ISK_IN CVA, CVB TA TJ 25 Min 9.0 -8.0 13.2 0 VEE + 3.5 VEE + 2.9 VEE + 3.5 .4 .6 0 VEE + 3.5 Max 15.5 -4.2 20.5 5.0 VCC - 2.9 VCC - 3.5 VCC - 2.0 1.3 1.25 1.65 VCC - 3.5 +70 +125 Units V V V V V V V mA mA mA V
oC oC
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Edge710
EDGE HIGH-PERFORMANCE PRODUCTS Absolute Maximum Ratings
Parameter VCC (relative to GND) VEE (relative to GND) Total Power Supply Digital Input Voltages Analog Input Voltages Analog Input Currents Digital Output Currents Driver Output Current Driver Swing Comparator Input Voltage Ambient Operating Temperature Storage Temperature Junction Temperature Soldering Temperature (5 seconds, .25" from the pin) Symbol VCC VEE VCC - VEE DHI(*), DVR_EN(*), LD_EN(*) CVA, CVB, DVH, DVL, VCM_IN ISC_IN, ISK_IN QA/QA*, QB/QB* Iout DVH - DVL CVA(B) - VINP TA TS TJ TSOL VEE VEE 0 0 -40 0 -13 -50 -65 Min 0 -10 Max 16.5 0 21.0 +7.0 VCC 3.0 50 +40 13 +13 +125 +150 +150 +260 Units V V V V V mA mA mA V V
oC oC oC oC
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these, or any other conditions beyond those listed, is not implied. Exposure to absolute maximum conditions for extended periods may affect device reliability.
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Edge710
EDGE HIGH-PERFORMANCE PRODUCTS DC Characteristics
Parameter LOAD Circuit Commutating Voltage Programmable Range Offset Voltage VCM_IN_A Current In Diff Voltage Range Load Output Output Voltage Range Output Current Range Load Enable Input Voltage Range Differential Input Swing Input Current Source Current Input Current ISC_IN Voltage Current Gain Sink Current Input Current ISK_IN Voltage Current Gain Load Linearity 0 mA <= Output < 5 mA 5 mA <= Output < 35 mA HiZ Leakage Current HiZ Compliance Source/Sink Bridge Resistance (measured @ I = 500 A) Source/Sink Error Cal Points
20 A / 30 A 30 A / 130 A 130 A / 500 A 500 A / 750 A 750 A / 1 mA 1 mA / 1.2 mA 1.2 mA / 1.4 mA 1.4 mA / 1.6 mA 1.6 mA / 1.8 mA
Symbol
Min
Typ
Max
Units
VCM_IN VCM_OUT_A - VCM_IN Iin LOAD - VCM_OUT_A V - LOAD I - LOAD LD_EN, LD_EN* LD_EN - LD_EN* Iin ISC_IN V_ISC_IN I_SOURCE/ ISC_IN ISK_IN V_ISK_IN I_SINK/ ISK_IN Actual - Programmed Actual - Programmed Ibias
VEE + 3.5 -100 -100 -10 VEE + 3.5 -35 -2.0 0.25 -100 0 -100 18.2 0 -100 18.2 -1A - 1% -50 -100 VEE + .5 .5
5
VCC - 3.5 +100 +100 +10 VCC - 3.5 +35 +5.0 4.0 +100 2.0 +100 21.8 2.0 +100 21.8 +1A + 1% +50
V mV A V V mA V V A mA mV
0 20
0 20
mA mV
A A nA V K
0
+100 VCC
1.0
2.0
Test Point 25 A 80 A 315 A 625 A 875 A 1.1 mA 1.3 mA 1.5 mA 1.7 mA
-(1% + 1) -(1% + 1) -50 -50 -50 -50 -50 -50 -50
1% + 1 1% + 1 +50 +50 +50 +50 +50 +50 +50
A A A A A A A A A
DC test conditions (unless otherwise specified): "Recommended Operating Conditions". RADJ = FADJ = 1.1 mA. BIAS = .6 mA.
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Edge710
EDGE HIGH-PERFORMANCE PRODUCTS DC Characteristics (continued)
Parameter COMPARATOR Circuit V_INP Leakage (IPD = 0) @ +8V @ +5V @ -2V @ -4V V_INP Leakage (IPD = 1) @ VEE + 3.5V @ VCC - 3.5V Offset Voltage (Note 1) IPD_C = 0 IPD_C = 1 Threshold Voltage Threshold Input Current Input Voltage Range Input Diffierential Range Differential Output Swing Common Mode Output (Note 2) Logical 1 Logical 0 POWER SUPPLIES Power Supply Consumption (Note 3) Positive Supply Negative Supply I_BIAS I_BIAS I_BIAS I_BIAS I_BIAS I_BIAS -2 -1 -1 -1 -250 -250 1 < +2 +1 +1 +1 +250 +250 A A A A nA nA Symbol Min Typ Max Units
100 < 100 <
Vos Vos CVA, CVB I_BIAS CVA(B) V_INP V_INP - CVA(B) |QA - QA*|, |QB - QB*|
-10 -10 VEE + 2.9 -50 VEE + 3.5 -12 400
+10 +10 VCC - 2.9 +50 VCC - 3.5 +8
mV mV V A V V mV
QA, QA*, QB, QB* QA, QA*, QB, QB*
PECL - 1.3 PECL - 1.8
PECL - 1.13 PECL - 1.64
PECL - 0.9 PECL - 1.4
V V
ICC IEE
120 -200
180 -160
mA mA
DC test conditions (unless otherwise specified): "Recommended Operating Conditions". RADJ = FADJ = 1.1 mA. BIAS = .6 mA. Note 1: This parameter is guaranteed by characterization. It is tested in production against 100 mV limits. Note 2: Tested at PECL = 0V, PECL = +4V. Note 3: No Load Conditions.
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Edge710
EDGE HIGH-PERFORMANCE PRODUCTS DC Characteristics (continued)
Parameter DRIVER Circuit A nalog I nput s Hig h Lev el Low Lev el Super V olt ag e Lev els Driv er Sw ing I nput C urrent Slew R at e A dj ust ment s C hip B ias C urrent Driv er Out put DC Out put C urrent Out put I mpedanc e ( @ 25 mA ) HiZ Leak ag e ( I P D_D = 0) HiZ Leak ag e ( I P D_D = 1) ( Not e 1) DC "Hig h" A c c urac y Offset V olt ag e Gain ( Not e 2) Linearit y ( -2V t o +7V ) Linearit y ( @ -3V , @ +8V ) DC "Low " A c c urac y Offset V olt ag e Gain ( Not e 3) Linearit y ( -3V t o +6V ) Linearit y ( @ -4V , @ +7V ) Dig it al I nput s I nput V olt ag e R ang e Different ial I nput Sw ing I nput C urrent Symbol Min Typ Max Units
DV H DV L DV H, DV L DV H - DV L I _in R A DJ, F A DJ BIA S
V EE + 3.5 V EE + 2.9 V EE + 3.5 0 - 50 0.4 .6
0.6
V C C - 2.9 V C C - 3.5 V C C - 2.0 9.0 +50 1.3 1.25
V V V V A mA mA
I max R out I bias I bias
-35 0.5 - 250 -5
+35 3.0 +250 +5
mA nA nA
DV H - DOUT DV H/ DOUT DV H - DOUT DV H - DOUT
- 100 .985 -10 -15
+100 1.0 +10 +15
mV V/ V mV mV
DV L - DOUT DV L/ DOUT DV L - DOUT DV L - DOUT
- 100 .985 - 10 - 15
+100 1.0 +10 +15
mV V/ V mV mV
DHI ( *) , DV R _EN( *) I nput - I nput * I in
- 2.0 0.25 - 350
+5.0 4.0 +350
V V A
Note 1: Note 2: Note 3:
This parameter is guaranteed by characterization. It is tested in production against 200 nA limits. Gain is computed from 2 points: DVH = -1V, +4V. Gain is computed from 2 points: DVL = -1V, +4V.
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Edge710
EDGE HIGH-PERFORMANCE PRODUCTS AC Characteristics
Parameter LOAD Circuit Propagation Delay Inhibit to Iout Iout to Inhibit Output Capacitance Load Active Load Off COMPARATOR Circuit Propagation Delay Input Slew Rate Tracking IPD_C = 0 IPD_C = 1 Input Capacitance Digital Output Rise and Fall Times (20% - 80%) Minimum Pulse Width DRIVER Circuit Propagation Delay Data to Output Enable to HiZ Enable to Output Active Rise/Fall Times 800 mV (20% - 80%) 3V (10% - 90%) 5V (10% - 90%) Fmax 800 mV 3V 5V Minimum Pulse Width 800 mV 3V 5V Output Capacitance Cout Tpd Tpd Tpd Tr/Tf Tr/Tf Tr/Tf Fmax Fmax Fmax 1.5 1.5 1.5 500 800 1.0 600 400 200 800 1.2 2.4 2.0 ns ns ns ps ps ns MHz MHz MHz ps ns ns pF Cin Tr, Tr Tpd 6.0 25 2.0 250 1.5 ns V/ns mV/ns pF ps Tpd_on Tpd_off Cout Cout 3 <.8 3.5 2.0 ns ns pF pF Symbol Min Typ Max Units
1.0
ns
DC test conditions (unless otherwise specified): "Recommended Operating Conditions". RADJ = FADJ = 1.1 mA. BIAS = .6 mA.
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Edge710
EDGE HIGH-PERFORMANCE PRODUCTS Ordering Information
Model Number
Package 52 Lead MQFP (10 mm x 10 mm Body) with Internal Heat Spreader Die Form
E710AHF
D710
EVM710AHF
Edge710 Evaluation Board
Contact Information
Semtech Corporation Edge High-Performance Division 10021 Willow Creek Rd., San Diego, CA 92131 Phone: (858)695-1808 FAX (858)695-2633
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